PLL: Yes with Bypass, 입력: HCSL, HSTL, LVDS, LVPECL, MLVDS, SSTL, 산출: HCSL, HSTL, LVDS, LVPECL, MLVDS, SSTL, 회로 수: 1, 비율-입력 : 출력: 2:6,
유형: Clock Generator, Fanout Distribution, Zero Delay Buffer, PLL: Yes with Bypass, 입력: HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, 산출: eHSTL, HSTL, LVCMOS, LVTTL, SSTL, 회로 수: 1, 비율-입력 : 출력: 2:20,
유형: Clock Generator, Fanout Distribution, Zero Delay Buffer, PLL: Yes with Bypass, 입력: HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, 산출: eHSTL, HSTL, LVCMOS, LVTTL, SSTL, 회로 수: 1, 비율-입력 : 출력: 2:12,
유형: Clock Generator, Fanout Distribution, Zero Delay Buffer, PLL: Yes with Bypass, 입력: HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, 산출: eHSTL, HSTL, LVCMOS, LVTTL, SSTL, 회로 수: 1, 비율-입력 : 출력: 2:16,
유형: Clock Generator, Fanout Distribution, Zero Delay Buffer, PLL: Yes with Bypass, 입력: HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, 산출: eHSTL, HSTL, LVCMOS, LVTTL, SSTL, 회로 수: 1, 비율-입력 : 출력: 2:4,
유형: Clock Generator, Fanout Distribution, Zero Delay Buffer, PLL: Yes with Bypass, 입력: HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, 산출: eHSTL, HSTL, LVCMOS, LVTTL, SSTL, 회로 수: 1, 비율-입력 : 출력: 2:8,
